SEQUENTIAL FUNCTION CHART VERIFICATION

SEQUENTIAL FUNCTION CHART VERIFICATION

Kluwer Academic Publishers, Dordrecht (2000)īauer, N., Huuck, R.: Towards automatic verification of embedded control software. Lampérière, S., Lesage, J.J.: Formal verification of the sequential part of PLC programs. Kowalewski, S., Engell, S., Preussig, J., Stursberg, O.: Verification of logic controllers for continuous plants using timed condition/event system models. Moon, I., Powers, G.J., Burch, J.R., Clarke, E.M.: Automatic verification of sequential control systems using temporal logic. 65: Programmable Controllers – Programming Languages, IEC 61131-3. International Electrotechnical Commission, Technical Committee No. Lewis, R.: Programming industrial control systems using IEC 61131-3. For different processing system examples, we illustrate the complete verification procedure consisting of controller specification, model transformation, integration of dynamic plant models, and identifying errors in the control program by model checking. While the first approach translates untimed SFC into the input language of the tool Cadence SMV, the second converts timed SFC into timed automata which can be analyzed by the tool Uppaal. We present two different approaches to convert SFC programs algorithmically into automata models that are amenable to model checking. To investigate the correctness of SFC programs with respect to a given set of requirements, this contribution advocates the use of formal verification. For the specification and the implementation of PLC programs, the graphical and hierarchical language Sequential Function Charts (SFC) is increasingly used in industry. Programmable Logic Controllers (PLC) are widespread in the manufacturing and processing industries to realize sequential procedures and to avoid safety-critical states.

Sequential function chart